1. Field of the Invention
The present invention relates to an active matrix display device, and particularly to an active matrix display device which includes a pixel unit comprising row-type gate lines, column-type signal lines and pixels arranged at respective intersecting portions of the row-type gate lines and the column-type signal lines, a vertical scan circuit for successively scanning the gate lines on a line basis to select pixels of one row every horizontal period, and a horizontal scan circuit for supplying video signals to the signal lines within one horizontal period and successively writing the video signals in the selected pixels of one row.
2. Description of the Related Art
A liquid crystal display has advantages in that it can be easily designed to be thin, power consumption is low and it can be easily designed to have a color display. It is widely used for a display screen of OA equipment or the like. Further, an active matrix liquid crystal display (AM-LCD: Active Matrix-Liquid Crystal Display) has been recently mainly used. In the active matrix liquid crystal display, switches such as a transistor, a diode, etc. which are used to apply a voltage are arranged on each display dot, and it is excellent in contrast, response speed, and color purity.
FIG. 1 is a diagram showing an active matrix liquid crystal display. The active matrix liquid crystal display includes gate lines G arranged on rows, signal lines S1, S2, S3, . . . arranged on columns, and matrix-arranged pixels PXL which are arranged at the intersecting portions of the gate lines and the signal lines.
Each pixel PXL is driven by a switching element which comprises a thin film transistor Tr, etc. The gate electrode of the thin film transistor Tr is connected to the corresponding gate line G, the source electrode is connected to the corresponding signal line S, and the drain electrode is connected to the corresponding pixel PXL.
The active matrix liquid crystal display contains a vertical scan circuit 10 and a horizontal scan circuit 20 in addition to the pixel PXL, etc. The vertical scan circuit 10 successively scans the respective gate lines G on a line by line basis, and selects pixels PXL of one row every horizontal period. That is, the vertical scan circuit 10 outputs a selected pulse to each gate line G every horizontal period to set the thin film transistor Tr on the same line to a conductive state.
Further, the horizontal scan circuit 20 successively samples the video signals from a video line to each signal line S1, S2, S3, . . . within one horizontal period to successively write the video signals into the selected pixels PXL of one row on a point basis. The horizontal scan circuit 20 has a shift register 20a comprising multistage-connected flip-flops FF.
The shift register 20a is actuated in accordance with a pair of horizontal clocks HCK, HCKX which are supplied from externally and have opposite phases to each other, and it successively transfers horizontal start signals HST supplied from externally to output sampling pulses A1, A2, A3, . . . every stage. On the basis of the sampling pulse A1, A2, A3, . . . , final sampling pulses B1, B2, B3, . . . are obtained through logic circuits 70a, 70b, 70c, . . . for waveform shaping.
The signal lines S1, S2, S3, . . . are connected to horizontal switches HSW1, HSW2, HSW3, . . . , respectively, and receive the incoming video signals through the common video line. The respective horizontal switches HSW1, HSW2, HSW3, . . . successively carry out the switching operation thereof in accordance with the corresponding sampling pulses B1, B2, B3, . . . respectively, and successively sample the video signals to the corresponding signal lines S1, S2, S3, . . .
FIG. 2 is a timing chart showing the operation of the active matrix liquid crystal display. The horizontal start signal HST is one-pulse. On the other hand, the horizontal clock signals HCK and HCKX are rectangular waves which are opposite in phase to each other. In accordance with these clock signals, the shift register 20a operates to successively transfer HST and successively output the sampling pulses A1, A2, A3, . . .
These sampling pulses A1, A2, A3, . . . are subjected to the waveform shaping by the logical circuits 70a, 70b, 70c, . . . which are provided at the respective stages of the shift register 20a, thereby obtaining the final sampling pulses B1, B2, B3, . . . which are timely separated from one another.
The horizontal switches HSW1, HSW2, HSW3, . . . successively carry out the switching operation in accordance with the sampling pulses B1, B2, B3, . . . to sample the video signals to the signal lines.
Accordingly, in order to set the voltage level of the video signal to the pixel PXL, it is necessary that the sampling pulses B1, B2, B3, . . . and the incoming video signals are matched with each other in phase.
However, the active matrix liquid crystal display has some dispersion between elements in a manufacturing process. Further, in the process of generating the sampling pulses B1, B2, B3, . . . a time delay accurst during a period from the leading (trailing) edge of HCK and HCKX until the output time of the sampling pulses A1, A2, A3, . . . from the shift register 20a, and until passing through the logical circuits 70a, 70b, 70c, . . . Accordingly, the phases of the sampling pulses B1, B2, B3, . . . are dispersed.
Therefore, the sampling is performed with a time lag from the original time at which the sampling must be originally performed, resulting in reduction of resolution and occurrence of ghost images. Accordingly, it is necessary to suppress the dispersion of phase among the sampling pulses.
FIG. 3 is a schematic diagram showing an active matrix liquid crystal display which eliminates the phase dispersion of the sampling pulses in the prior art. The basic construction is the same as the active matrix liquid crystal display as shown in FIG. 1, and it includes gate lines G arranged on rows, signal lines S arranged on columns and pixels PXL arranged in a matrix form at the respective intersecting portions of the gate lines and the signal lines. Further, it contains a vertical scan circuit 10 to successively scan the gate lines G on a line basis and select pixels PXL of one row every horizontal period. Further, it contains a horizontal scan circuit 20 to supply the video signals to the respective signal lines within one horizontal period and successively write the video signals in the selected pixels PXL of one row on a point basis.
Further, as a characteristic construction, a clock switch CKSW is provided to the output of the shift register 20a. CKSW performs its switching operation in accordance with a sampling pulse A which is connected to the shift register 20a, and samples CK, CKX which are the same as or different from HCK, HCKX, thereby generating sampling pulses B.
The horizontal switch HSW is connected to one end of each signal line S, and performs the switching operation in accordance with the sampling pulse B to successively sample the video signals input to the signal lines.
FIG. 4 is a timing chart showing the operation of the active matrix liquid crystal display which eliminates the phase dispersion of the sampling pulses. The horizontal start signal a one-shot pulse. On the other hand, the horizontal clock signals HCK, HCKX are rectangular waves which are opposite in phase to each other, and the shift register 20a is operated in accordance with these signals to successively transfer HST and output the sampling pulse A.
CK and CKX are rectangular waves which are opposite in phase to each other. HCK and CK, and HCKX and CKX have the same waveform, and they may be commonly used. CKSW performs the switching operation in accordance with the sampling pulse A to pick up one or plural CKX pulses or CK pulses contained in the sampling pulse A. In the figure, one CKX pulse contained in the sampling pulse A is picked up to generate the sampling pulse B.
As described above, the sampling pulse B to drive HSW is picked up from the original clock signal CK or CKX, so that the dispersion thereof is less than the sampling pulse A.
However, in the above-described prior art, when the sampling pulse A which is an output of the shift register 20a and CKX are deviated from each other in phase, dispersion occurs in phase between the sampling pulses B.
FIG. 5 is a timing chart showing occurrence of phase dispersion of the sampling pulses B. The sampling pulse A and CKX are deviated in phase by t.
The sampling pulse B is taken out as the CKX pulse contained in the sampling pulse A, so that when the sampling pulse A is off as shown in the figure, the sampling pulse B is also off.
Accordingly, when the sampling pulse A is dispersed, the sampling pulse B is also dispersed in phase. This phase dispersion induces reduction of resolution, ghost, etc.